The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices having thyristor-based devices and to thyristor-based memory.
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F2 and 8 F2, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F2 and 100 F2.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in overcoming many previously unresolved problems for thyristor-based applications. An important consideration in the design of the thin capacitively-coupled thyristor device involves designing the body of the thyristor sufficiently thin, so that capacitive coupling between a control port and a thyristor base region can substantially modulate the potential of the base region. Another important consideration for thyristors used in such NDR devices is to ensure tight control over the conductance state of the thyristor.
These and other design considerations have presented challenges to implement such a thin capacitively-coupled thyristor in a variety of circuit implementations.
The present invention is directed to overcoming the above-mentioned challenges and others related to the types of devices and applications discussed above and in other thyristor-based semiconductor applications, such as memory cells and embedded memory applications. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a thyristor-based semiconductor device is manufactured having contiguously adjacent base and emitter regions having a junction therebetween, with a portion of the emitter region extending along and adjacent to the junction being lightly doped, relative to the adjacent base region. In connection with this example embodiment, it has been discovered that light doping results in decreased electric field between the base and emitter region. This decreased electric field has been found to be particularly useful in memory applications, wherein the thyristor is used for data storage. With this approach, such a thyristor-based semiconductor device can be implemented in a variety of applications, wherein tight control over the operation of the thyristor, and thus the storage of data, can be maintained.
In a more particular example embodiment of the present invention, a pass device is coupled in series to a second emitter region of the thyristor. A control port is arranged for capacitively coupling a signal to a second base region of the thyristor and for controlling current flow therein. A reference voltage line is coupled to the emitter region with a lightly-doped portion, and in response to signals (i.e., voltages) applied to the control port and the pass device, current flow in the thyristor, and thus the state of the second emitter region, is controlled. The controlled state of the second emitter region is used for storing data therein.
In another example embodiment of the present invention, a memory circuit arrangement includes an array of memory cells adapted for storing data. At least some of the memory cells include a thyristor having an emitter region with a relatively lightly-doped region, a pass device and control port as discussed above. The control ports of the cells and the pass devices are coupled to word lines adapted for applying the signals to the thyristors and pass devices for controlling data storage and manipulation at the thyristor.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.